ATPG USE TETRAMAX 思维图

ATPG – use TetraMax
   关于ATPG
       ATPG:automatic test pattern generation(自动生成测试模式）
       ATE：automatic test equipment(自动测试设备）
   TMAX ATPG Flow
       名词解释
           stil：standard test interfance language (标准测试接口语言)
           spf：STIL procedure file(STIL过程文件）
           wgl：waveform generation language (波形产出语言）
       flow
           Read Library Modules
           Read Netlist
           Build ATPG model
           Check DFT rules
           Run ATPG
           Check result and Save patterns
   1、Start TeartMax
       GUI mode：tmax -tcl -gui
       Command mode：tmax -tcl -shell
       Execute tcl script after TMAX started : source -echo -verbose atpg.tcl
       GUI mode on/off after TMAX started : gui_start gui_stop
   2、Read Library Models：set_message -log tmax.log -replace
       read_netlist -verbose -library smic18.v
read_netlist -verbose -library pad.v
read_netlist -verbose -library sram.v
read_netlist -verbose -library rom.v
注意：RAM/ROM/Analog模块使用verilog模块，没有功能描述。
   3、Read Netlist :Read in design netlist
       read_netlist -verbose my_design.v
       set TOP_DESIGN my_design
       report_modules -error -undefined
   4、Build ATPG model ：build test model for the desig
       set_build -black_box sram
           设置模式sram为黑盒
       run_build_model ${TOP_DESIGN}
   5、Run ATPG：prepare and run ATPG
       set_faluts -model stuck
           生成标准的ATPG模式
       set_faults -summary verbose
           显示详细的摘要报告
       set_faults -fault_coverage
           在总结报告中汇报故障覆盖率
       set_patterns -internal
           模式源是内部生成的
       set_atpg -verbose
           在模式合并期间显示详细信息
       set_atpg -coverage 100
           将测试覆盖率目标设置为终止
       run_atpg -auto_compression
   6、check result and save patterns
       check ATPG result
           set_faults -report collapsed

report_summaries

set_faults -report uncollapsed

report_sumaries > ../rpt/$TOP_DESIGN_summary.rpt

report_faults -level 3 -class all -uncollapsed -verbose
<hierarchical &verbose report >–分层和详细报告

report_scan_chains -verbose > ../rpt$TOP_DESIGN_scan_chain.rpt

report_scan_cells -all ../rpt/$TOP_DESIGN_scan_cell.rpt
save test patterns
write_patterns -format stil99 -serial -cellnames verilog -replace \\
> ../patterns/$TOP_DESIGN.stil

write_patterns -format wgl -serial -replace \\
> ../patterns/$TOP_DESIGN.stil

<stil or wgl used for ATE testing >–stil 或者wgl 用于ATE 测试

write patterns -format stil -verilog_test_bench_name $TOP_MODULE_test \\
-serial > ../pattern/$STOP_DESIGN.v

< verilog file used for simulation the pattern>–用于模拟模式的verilog文件
7、ATPG results